The invention relates to the field of computerized system science, and more specifically, to dynamic logic gates and to dynamic logic cascades comprising such dynamic logic gates.
It is known to use complementary metal oxide semiconductor (CMOS) and silicon on insulator (SOI) for constructing dynamic logic gates. FIG. 1 shows an example of a two input AND dynamic logic gate 10 designed with CMOS/SOI technology. The dynamic logic gate 10 of FIG. 1 comprises: a first CMOS 12 whose gate is connected to a clock signal clk; a second CMOS 14 whose gate is supplied with a first input signal B to be added to a second input signal A, and whose source electrode is connected to the drain electrode of the first CMOS 12; a third CMOS 16 whose gate is supplied with the second input signal A, whose source electrode is connected to the drain electrode of the second CMOS 14, and whose source electrode is connected to the drain electrode of a fourth CMOS 18, wherein the gate of the fourth CMOS 18 is supplied with a complementary clock signal clk (complementary to the clock signal clk).
The drain electrode of the third CMOS 16 is connected to an operational amplifier (also known as inverter) 20 so as to ensure output signal level of the dynamic logic gate 10.
Such dynamic logic gates may be used in microprocessors, microcontrollers and other digital logic circuits.
It is known that a dynamic logic gate as the one illustrated on FIG. 1 suffers from a leakage current (represented by arrow 22) which limits the scaling of CMOS' threshold voltage Vt—below which the current through a CMOS drops exponentially—and supply voltage Vdd. The leakage current thus prevents lowering energy per computing operation. Moreover, this type of dynamic gate is very sensitive to noise.
To limit the leakage current in a dynamic logic gate of the type exemplified in FIG. 1, it is known to add a further keeper (also known as “bleeder”) CMOS 24. However, adding a further CMOS device complicates the circuit and goes against miniaturization thereof.